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solidswitch9 2.2.0
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Settings for registers of SolidSwitch 9 Click driver. More...
Settings for registers of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_ADC9SR_ADC9SR_MASK 0x3FF0 |
SolidSwitch 9 ADC9SR registers setting.
Specified setting for ADC9SR registers of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_ADC9SR_UPDTSR 0x0002 |
| #define SOLIDSWITCH9_ADCXSR_ADCXSR_MASK 0x3FF0 |
SolidSwitch 9 ADCxSR registers setting.
Specified setting for ADCxSR registers of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_ADCXSR_SOCRX_EN 0x0004 |
| #define SOLIDSWITCH9_ADCXSR_UPDTSR 0x0002 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH0_16MS 0x0010 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH0_240MS 0x00F0 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH0_32MS 0x0020 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH0_LATCH_OFF 0x0000 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH0_MASK 0x00F0 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH1_16MS 0x0100 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH1_240MS 0x0F00 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH1_32MS 0x0200 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH1_LATCH_OFF 0x0000 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH1_MASK 0x0F00 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH2_16MS 0x1000 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH2_240MS 0xF000 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH2_32MS 0x2000 |
| #define SOLIDSWITCH9_CHLOFFTCR0_CH2_LATCH_OFF 0x0000 |
SolidSwitch 9 CHLOFFTCR0 register setting.
Specified setting for CHLOFFTCR0 register of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_CHLOFFTCR0_CH2_MASK 0xF000 |
| #define SOLIDSWITCH9_CHLOFFTCR1_CH3_16MS 0x0010 |
| #define SOLIDSWITCH9_CHLOFFTCR1_CH3_240MS 0x00F0 |
| #define SOLIDSWITCH9_CHLOFFTCR1_CH3_32MS 0x0020 |
| #define SOLIDSWITCH9_CHLOFFTCR1_CH3_LATCH_OFF 0x0000 |
SolidSwitch 9 CHLOFFTCR1 register setting.
Specified setting for CHLOFFTCR1 register of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_CHLOFFTCR1_CH3_MASK 0x00F0 |
| #define SOLIDSWITCH9_CTRL_CTDTH_120C 0x0000 |
| #define SOLIDSWITCH9_CTRL_CTDTH_130C 0x1000 |
| #define SOLIDSWITCH9_CTRL_CTDTH_140C 0x2000 |
| #define SOLIDSWITCH9_CTRL_CTDTH_MASK 0x3000 |
| #define SOLIDSWITCH9_CTRL_EN 0x0800 |
| #define SOLIDSWITCH9_CTRL_GOSTBY 0x8000 |
SolidSwitch 9 CTRL register setting.
Specified setting for CTRL register of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_CTRL_LOCKEN_CCRX 0x0020 |
| #define SOLIDSWITCH9_CTRL_LOCKEN_CHLOFFTCRX 0x0008 |
| #define SOLIDSWITCH9_CTRL_LOCKEN_CHPHAX 0x0010 |
| #define SOLIDSWITCH9_CTRL_LOCKEN_MASK 0x007C |
| #define SOLIDSWITCH9_CTRL_LOCKEN_PWM_CLK_SYNC 0x0004 |
| #define SOLIDSWITCH9_CTRL_LOCKEN_SLOPECRX 0x0040 |
| #define SOLIDSWITCH9_CTRL_PWM_TRIG_FALLING 0x0400 |
| #define SOLIDSWITCH9_CTRL_PWM_TRIG_MASK 0x0400 |
| #define SOLIDSWITCH9_CTRL_PWM_TRIG_RISING 0x0000 |
| #define SOLIDSWITCH9_CTRL_PWMSYNC 0x0002 |
| #define SOLIDSWITCH9_CTRL_UNLOCK 0x4000 |
| #define SOLIDSWITCH9_DEF_DUTY_CYCLE 0.5 |
| #define SOLIDSWITCH9_DEF_FREQ 400000 |
SolidSwitch 9 default PWM frequency.
Specified setting for default PWM frequency of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_GSB_FAIL_SAFE 0x01 |
| #define SOLIDSWITCH9_GSB_GSBN 0x80 |
SolidSwitch 9 global status byte setting.
Specified setting for global status byte of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_GSB_LOFF 0x04 |
| #define SOLIDSWITCH9_GSB_OLOFF 0x02 |
| #define SOLIDSWITCH9_GSB_OT_PL_VDS 0x10 |
| #define SOLIDSWITCH9_GSB_RESET 0x40 |
| #define SOLIDSWITCH9_GSB_SPI_ERROR 0x20 |
| #define SOLIDSWITCH9_GSB_T_CASE 0x08 |
| #define SOLIDSWITCH9_INFO_COMPANY_CODE 0x00 |
SolidSwitch 9 device info setting.
Specified setting for device info of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_INFO_DEVICE_FAMILY 0x01 |
| #define SOLIDSWITCH9_INFO_PRODUCT_CODE_1 0x58 |
| #define SOLIDSWITCH9_INFO_PRODUCT_CODE_2 0x56 |
| #define SOLIDSWITCH9_INFO_PRODUCT_CODE_3 0x61 |
| #define SOLIDSWITCH9_OUT0 0x01 |
| #define SOLIDSWITCH9_OUT1 0x02 |
| #define SOLIDSWITCH9_OUT2 0x04 |
| #define SOLIDSWITCH9_OUT3 0x08 |
SolidSwitch 9 output setting.
Specified setting for output of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_OUT_DUTY_0_PCT 0x0000 |
| #define SOLIDSWITCH9_OUT_DUTY_100_PCT 0x03FF |
| #define SOLIDSWITCH9_OUT_DUTY_10_PCT 0x0066 |
| #define SOLIDSWITCH9_OUT_DUTY_15_PCT 0x0099 |
| #define SOLIDSWITCH9_OUT_DUTY_20_PCT 0x00CC |
| #define SOLIDSWITCH9_OUT_DUTY_25_PCT 0x0100 |
| #define SOLIDSWITCH9_OUT_DUTY_30_PCT 0x0133 |
| #define SOLIDSWITCH9_OUT_DUTY_35_PCT 0x0166 |
| #define SOLIDSWITCH9_OUT_DUTY_40_PCT 0x0199 |
| #define SOLIDSWITCH9_OUT_DUTY_45_PCT 0x01CC |
| #define SOLIDSWITCH9_OUT_DUTY_50_PCT 0x0200 |
| #define SOLIDSWITCH9_OUT_DUTY_55_PCT 0x0233 |
| #define SOLIDSWITCH9_OUT_DUTY_5_PCT 0x0033 |
| #define SOLIDSWITCH9_OUT_DUTY_60_PCT 0x0266 |
| #define SOLIDSWITCH9_OUT_DUTY_65_PCT 0x0299 |
| #define SOLIDSWITCH9_OUT_DUTY_70_PCT 0x02CC |
| #define SOLIDSWITCH9_OUT_DUTY_75_PCT 0x0300 |
| #define SOLIDSWITCH9_OUT_DUTY_80_PCT 0x0333 |
| #define SOLIDSWITCH9_OUT_DUTY_85_PCT 0x0366 |
| #define SOLIDSWITCH9_OUT_DUTY_90_PCT 0x0399 |
| #define SOLIDSWITCH9_OUT_DUTY_95_PCT 0x03CC |
| #define SOLIDSWITCH9_OUT_MASK 0x0F |
| #define SOLIDSWITCH9_OUTCFGRX_CCR_BULB 0x0000 |
| #define SOLIDSWITCH9_OUTCFGRX_CCR_LED 0x0008 |
| #define SOLIDSWITCH9_OUTCFGRX_CCR_MASK 0x0008 |
| #define SOLIDSWITCH9_OUTCFGRX_CHPHA_MASK 0x1F00 |
| #define SOLIDSWITCH9_OUTCFGRX_CPCR_CONTINUOUS 0x0080 |
| #define SOLIDSWITCH9_OUTCFGRX_CPCR_FILTERED 0x00C0 |
| #define SOLIDSWITCH9_OUTCFGRX_CPCR_MASK 0x00C0 |
| #define SOLIDSWITCH9_OUTCFGRX_CPCR_START 0x0040 |
| #define SOLIDSWITCH9_OUTCFGRX_CPCR_STOP 0x0000 |
| #define SOLIDSWITCH9_OUTCFGRX_DIENCR_EN 0x0004 |
| #define SOLIDSWITCH9_OUTCFGRX_PWMFCY_1024 0x0000 |
| #define SOLIDSWITCH9_OUTCFGRX_PWMFCY_2048 0x0010 |
| #define SOLIDSWITCH9_OUTCFGRX_PWMFCY_4096 0x0020 |
| #define SOLIDSWITCH9_OUTCFGRX_PWMFCY_512 0x0030 |
| #define SOLIDSWITCH9_OUTCFGRX_PWMFCY_MASK 0x0030 |
| #define SOLIDSWITCH9_OUTCFGRX_SLOPECR_FAST 0x4000 |
| #define SOLIDSWITCH9_OUTCFGRX_SLOPECR_FASTER 0x8000 |
| #define SOLIDSWITCH9_OUTCFGRX_SLOPECR_FASTEST 0xC000 |
| #define SOLIDSWITCH9_OUTCFGRX_SLOPECR_MASK 0xC000 |
| #define SOLIDSWITCH9_OUTCFGRX_SLOPECR_STANDARD 0x0000 |
SolidSwitch 9 OUTCFGRx registers setting.
Specified setting for OUTCFGRx registers of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_OUTCFGRX_VDSMASK 0x0002 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_0_PCT 0x0000 |
SolidSwitch 9 OUTCTRCRx registers setting.
Specified setting for OUTCTRCRx registers of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_100_PCT 0x3FF0 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_10_PCT 0x0660 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_15_PCT 0x0990 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_20_PCT 0x0CC0 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_25_PCT 0x1000 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_30_PCT 0x1330 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_35_PCT 0x1660 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_40_PCT 0x1990 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_45_PCT 0x1CC0 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_50_PCT 0x2000 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_55_PCT 0x2330 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_5_PCT 0x0330 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_60_PCT 0x2660 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_65_PCT 0x2990 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_70_PCT 0x2CC0 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_75_PCT 0x3000 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_80_PCT 0x3330 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_85_PCT 0x3660 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_90_PCT 0x3990 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_95_PCT 0x3CC0 |
| #define SOLIDSWITCH9_OUTCTRCRX_DUTY_CR_MASK 0x3FF0 |
| #define SOLIDSWITCH9_OUTCTRCRX_OLOFFCR_EN 0x0004 |
| #define SOLIDSWITCH9_OUTCTRCRX_WDTB 0x0002 |
| #define SOLIDSWITCH9_OUTSRX_CHFBSRX 0x1000 |
| #define SOLIDSWITCH9_OUTSRX_CHLOFFSRX 0x0100 |
| #define SOLIDSWITCH9_OUTSRX_DIENSR 0x8000 |
SolidSwitch 9 OUTSRx registers setting.
Specified setting for OUTSRx registers of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_OUTSRX_DIOTP0 0x2000 |
| #define SOLIDSWITCH9_OUTSRX_DIOTP1 0x4000 |
| #define SOLIDSWITCH9_OUTSRX_OLPUSRX 0x0200 |
| #define SOLIDSWITCH9_OUTSRX_PWMCLOCKLOW 0x0020 |
| #define SOLIDSWITCH9_OUTSRX_RST 0x0080 |
| #define SOLIDSWITCH9_OUTSRX_SPIE 0x0040 |
| #define SOLIDSWITCH9_OUTSRX_STKFLTRX 0x0400 |
| #define SOLIDSWITCH9_OUTSRX_VCCUV 0x0010 |
| #define SOLIDSWITCH9_OUTSRX_VDSFSRX 0x0800 |
| #define SOLIDSWITCH9_SET_DATA_SAMPLE_EDGE SET_SPI_DATA_SAMPLE_EDGE |
Data sample selection.
This macro sets data samples for SPI modules.
| #define SOLIDSWITCH9_SET_DATA_SAMPLE_MIDDLE SET_SPI_DATA_SAMPLE_MIDDLE |
| #define SOLIDSWITCH9_SOCR_CH0_EN 0x0100 |
| #define SOLIDSWITCH9_SOCR_CH1_EN 0x0200 |
| #define SOLIDSWITCH9_SOCR_CH2_EN 0x0400 |
| #define SOLIDSWITCH9_SOCR_CH3_EN 0x0800 |
SolidSwitch 9 SOCR register setting.
Specified setting for SOCR register of SolidSwitch 9 Click driver.
| #define SOLIDSWITCH9_SOCR_CHX_MASK 0x0F00 |
| #define SOLIDSWITCH9_SOCR_WDTB 0x0002 |